1. Field of the Invention
The invention relates to an isolation structure, and more particularly to a high-voltage device having a doped region between two isolation structures.
2. Description of the Prior Art
In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as vertical double-diffusion metal-oxide-semiconductor (VDMOS), insulated gate bipolar transistor (IGBT) and lateral diffusion MOS (LDMOS), is employed to increase power switching efficiency and decrease the loss of energy resources. It is often required that the switching transistors withstand high breakdown voltages and operate at a low on-resistance.
In current high-voltage device fabrication, multiple dummy gate patterns are often formed on shallow trench isolations (STIs) to accommodate the needs of wiring redistribution. These dummy gate patterns and the doped regions within the substrate however not only reduce the isolation effect of the STI, but also induce current leakage when voltages are applied. Hence, how to improve the current high-voltage device architecture has become an important task in this field.